FIGS. 1 to 4 are cross-section views showing triac-type high-voltage power components having a vertical structure. The triacs of these various drawings differ by their periphery.
Generally, the drawings show a triac formed from a lightly-doped N-type substrate 1 (N−). The upper and lower surfaces of substrate 1 comprise P-type doped layers or wells 3 and 4. Upper layer 3 contains a heavily-doped N-type region 5 (N+) and lower layer 4 contains a heavily-doped N-type region 6 (N+) in an area substantially complementary to that taken up, in top view, by region 5. Main electrodes A1 and A2 are respectively arranged on the upper surface and on the lower surface of substrate 1. According to cases, electrode A2 extends on all or part of the lower surface of substrate 1. The structure also comprises, on its upper surface side, a gate region topped with a gate electrode (not shown).
FIG. 1 shows a triac in mesa technology. P-type layers 3 and 4 respectively extend over the entire upper surface and over the entire lower surface of a lightly-doped N-type substrate 1 (N−). A ring-shaped groove is formed at the periphery of the upper surface of the triac and penetrates deeper into substrate 1 than layer 3. Similarly, a groove is formed at the periphery of the lower surface of the triac and penetrates deeper into substrate 1 than layer 4. The grooves are filled with a passivation glass 9, forming a glassivation. The PN junctions between each of P-type layers 3 and 4 and N−-type substrate 1 emerge onto glass 9. Main electrodes A1 and A2 are respectively arranged on the upper surface and on the lower surface of the triac.
FIG. 2 shows a triac in planar technology. P-type wells 3 and 4 are formed in lightly-doped N-type silicon substrate 1 (N−), respectively on the upper surface side and on the lower surface side of substrate 1. The upper and lower peripheries of the triac thus correspond to substrate 1. Main electrodes A1 and A2 are respectively arranged on well 3 and on well 4. An insulating layer 11 is arranged on portions of the lower and upper surfaces of the triac which are not covered by electrodes A1 and A2. Heavily-doped N-type channel stop rings 13 and 14 (N+) are formed in substrate 1, respectively at the periphery of the upper surface and at the periphery of the lower surface of the triac.
FIG. 3 shows a triac in “planar well” technology. The component of FIG. 3 differs from that in FIG. 2 in that it is surrounded by a P-type diffused wall 15. The lower surface of the triac is totally coated with a main electrode A2 and a P-type layer 4 extends over the entire lower surface of substrate 1 all the way to wall 15. A P-type well 3 extends on the upper surface side of the triac and stops before diffused wall 15. A channel stop ring 13 is arranged in substrate 1 between well 3 and wall 15. A ring-shaped electrode 17 may coat channel stop ring 13.
FIG. 4 shows a variation of a triac in “planar well” technology such as described in relation with FIG. 2 of French Application for Patent No. 1254987 filed on May 30, 2012 (incorporated by reference). The triac of FIG. 4 differs from the triac of FIG. 3 in that, on its lower surface side, a lower portion of diffused peripheral wall 15 which surrounds the component has been turned into insulating porous silicon forming an insulating ring 19. Porous silicon insulating ring 19 penetrates into substrate 1 down to a depth greater than the thickness of layer 4.
Each of the triacs of FIGS. 1 to 4 has various advantages and disadvantages.
In practice, in the mesa-type structure of FIG. 1, the steps of etching the grooves, of filling the grooves with passivation glass 9, and of cutting passivation glass 9 are difficult to implement.
In the planar structure of FIG. 2, a disadvantage is linked to the component assembly step. Indeed, if electrode A2 is desired to be soldered to a plate, lateral solder wickings may electrically connect electrode A2 to substrate 1, thus short-circuiting the corresponding PN− junction. It is thus necessary to assemble the component on a pad, which makes the assembly more complicated.
In the “planar well” structures of FIGS. 3 and 4, wall 15 isolates N−-type substrate 1 from possible solder wickings on the lateral surfaces of the triac on assembly thereof. However, the structures of FIGS. 3 and 4 require forming lateral wall 15 by diffusion of dopant elements from the lower and upper surfaces of substrate 1. A disadvantage is that this step is long, typically in the order of 250 hours for a substrate having a thickness from 200 to 300 μm and a boron doping. Further, it is necessary to provide an additional space at the triac periphery to form lateral wall 15, lateral wall 15 extending across a width in the order of the thickness of substrate 1.
The guard distance, that is, the distance necessary between the component edge and the edge of the useful portion of the component, depends on the type of periphery involved. For example, for a breakdown voltage in the order of 800 volts:                guard distance e1 of the structure of FIG. 1 is in the order of 300 μm,        guard distance e2 of the structure of FIG. 2 is in the order of 200 μm, and        guard distance e3 of the structures of FIGS. 3 and 4 is in the order of 400 μm.        